// *********************************************************************************
// Project Name : zkx2024
// Author       : Jlan
// Email        : 15533610762@163.com
// Create Time  : 2024-05-15
// File Name    : .v
// Module Name  :
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-15    Macro           1.0                     Original
//  
// *********************************************************************************

module dp_sram_share#(
    parameter integer DEPTH = 8192, // Depth of the SRAM
    parameter integer WIDTH = 36    // Width of the data bus
)(
    input wire clk,                  // Clock signal
    srammux_sram_bus.sram sram_bus
);

// Memory array to simulate the storage of the SRAM
reg [WIDTH-1:0] mem [0:DEPTH-1];

// Write operation block
always @(posedge clk) begin
    if (sram_bus.CS && sram_bus.WR) begin
        mem[sram_bus.W_ADDR] <= sram_bus.W_DATA; // Write data to the memory array at the address 'addr'
    end
end

// Read operation block
always @(posedge clk) begin
    if (sram_bus.CS && sram_bus.RD) begin
        sram_bus.R_DATA <= mem[sram_bus.R_ADDR]; // When not in output enable mode, read data from the memory array
    end else if (!sram_bus.CS || !sram_bus.RD) begin
        // When in high-Z mode (chip select high or output enable high), keep sram_bus.R_DATA in high impedance
        // 'bx represents a value that is unknown or not driven
        sram_bus.R_DATA <= 'bx;
    end
end

endmodule
